
`include "defines.v"

module ysyx_210448_regfile(
    input wire clk,
	input wire rst,
	input wire read,
	input wire ld,
	input wire [63:0]read_data,
	input wire [4:0] w_addr,
	input wire [`REG_BUS] data,
	input wire w_ena,
	input wire [4:0] rs1,
	input wire [4:0] rs2,
	input wire ena1,
	input wire ena2,
	output reg [`REG_BUS] op1,
	output reg [`REG_BUS] op2,
	output wire [`REG_BUS] regs_o[0 : 31]// difftest
    );
wire  [`REG_BUS] w_data;
assign w_data=(read==1'b1)?read_data:data;//判断存的数据是从mem中取的还是exe的计算值
reg [`REG_BUS] 	regs[0 : 31];
always @(posedge clk) 
	begin
		if (rst==1'b1) 
		begin
			regs[ 0] <= `ZERO_WORD;
			regs[ 1] <= `ZERO_WORD;
			regs[ 2] <= `ZERO_WORD;
			regs[ 3] <= `ZERO_WORD;
			regs[ 4] <= `ZERO_WORD;
			regs[ 5] <= `ZERO_WORD;
			regs[ 6] <= `ZERO_WORD;
			regs[ 7] <= `ZERO_WORD;
			regs[ 8] <= `ZERO_WORD;
			regs[ 9] <= `ZERO_WORD;
			regs[10] <= `ZERO_WORD;
			regs[11] <= `ZERO_WORD;
			regs[12] <= `ZERO_WORD;
			regs[13] <= `ZERO_WORD;
			regs[14] <= `ZERO_WORD;
			regs[15] <= `ZERO_WORD;
			regs[16] <= `ZERO_WORD;
			regs[17] <= `ZERO_WORD;
			regs[18] <= `ZERO_WORD;
			regs[19] <= `ZERO_WORD;
			regs[20] <= `ZERO_WORD;
			regs[21] <= `ZERO_WORD;
			regs[22] <= `ZERO_WORD;
			regs[23] <= `ZERO_WORD;
			regs[24] <= `ZERO_WORD;
			regs[25] <= `ZERO_WORD;
			regs[26] <= `ZERO_WORD;
			regs[27] <= `ZERO_WORD;
			regs[28] <= `ZERO_WORD;
			regs[29] <= `ZERO_WORD;
			regs[30] <= `ZERO_WORD;
			regs[31] <= `ZERO_WORD;
		end
		else 
		begin
			if (((w_ena==1'b1)|(read==1'b1)) && (w_addr!=5'h00))
			begin
				regs[w_addr] <=w_data;
			end
		end
	end

always @(*) begin
		if (rst == 1'b1)
			op1=`ZERO_WORD;
		else if (ena1 == 1'b1)
		begin
			op1=regs[rs1];
		end
		else if(ld)
		begin
			op1=regs[rs1];
		end
		else
			op1=`ZERO_WORD;
	end
	
always @(*) begin
	if (rst == 1'b1)
			op2=`ZERO_WORD;
		else if (ena2 == 1'b1)
		begin
			op2=regs[rs2];
		end
		else if(ld)
		begin
			op2=regs[rs2];
		end
		else
			op2=`ZERO_WORD;
	end

	genvar i;
	generate
		for (i = 0; i < 32; i = i + 1) begin
			assign regs_o[i] = (w_ena & w_addr == i & i != 0) ? w_data : regs[i];
		end
	endgenerate
	
endmodule
